マイクロン・テクノロジーメモリ
Semiconductor Principal Design Engineer
- 勤務地東京都
- デバイス・プロセス・設計アナログ・ミックスドシグナル・RF回路設計
- 中途
公式ページ 2026/09/11 時点当サイト掲載 2026/09/11
仕事内容
Responsibilities
Design and optimize TSV(Through-Silicon Via) interface circuits connecting memory die to logic die including Rx/Tx circuit for internal TSV channels, impedance matching and timing margin analysis. Develop and characterize TSV electrical models and define circuit design constraints for datapath interface. Define and implement signal integrity
応募条件
必須
- for the TSV channel, including eye margin, crosstalk, and noise budget analysis Define and implement power integrity
- using TSV for highly parallel IO and array operations Design and verify TSV-specific DFT (Design for Testability) circuits including loopback test modes, TSV continuity checks, and lane redundancy/remapping logic Interface with process technology and DTCO teams to optimize TSV design rules, standard cell usage, and layout strategies for the internal datapath Develop and execute functional verification plan for TSV interface and internal parallel bus including full chip circuit simulation and Verilog regression Design and optimize the wide internal parallel data bus spanning multiple arrays, channels and pseudo-channels, ensuring timing closure and signal integrity across the full parallel bus Architect the data path from the page buffer through da
募集要項の原文
Requirements for the TSV channel, including eye margin, crosstalk, and noise budget analysis Define and implement power integrity Requirements using TSV for highly parallel IO and array operations Design and verify TSV-specific DFT (Design for Testability) circuits including loopback test modes, TSV continuity checks, and lane redundancy/remapping logic Interface with process technology and DTCO teams to optimize TSV design rules, standard cell usage, and layout strategies for the internal datapath Develop and execute functional verification plan for TSV interface and internal parallel bus including full chip circuit simulation and Verilog regression Design and optimize the wide internal parallel data bus spanning multiple arrays, channels and pseudo-channels, ensuring timing closure and signal integrity across the full parallel bus Architect the data path from the page buffer through da
勤務条件
- 勤務地
- 東京都