TSMCファウンドリー
Layout Engineer
- 勤務地神奈川県横浜市 / 大阪府大阪市
- デバイス・プロセス・設計フィジカル設計・レイアウト
- 中途
仕事内容
Job Description
RDR design rules optimization. - Develop Standard Cell/IO Library Memory and Analog IPs in advanced technology. - Develop Memory IPs, Compiler and Test Vehicle. - Develop Standard Cell/IO Library and Analog. IPs - Provide design rules trade-off on area and performance. - Find layout solution for Standard Cell/IO Library Memory and Analog IPs to reduce RDR impact on area.
Background
will be a plus. - Highly welcome candidates who have less custom layout experience but have good related design experience, working attitude and are self-motivated. - Good command...
応募条件
必須
- BCH and above degree in EE or Engineering related field with 3+ years of working experiences.
- Expertise on std.
- Cell, SRAM, IO and analog layout and familiar with customers usage on those IPs.
- Layout expertise of SRAM (first priority), Standard cell, IO, Analog, Process with Virtuoso and Device
募集要項の原文
Qualifications - BCH and above degree in EE or Engineering related field with 3+ years of working experiences. - Expertise on std. Cell, SRAM, IO and analog layout and familiar with customers usage on those IPs. - Layout expertise of SRAM (first priority), Standard cell, IO, Analog, Process with Virtuoso and Device
勤務条件
- 勤務地
- 神奈川県横浜市 / 大阪府大阪市