TSMCファウンドリー
APR/Physical Design Engineer
- 勤務地神奈川県横浜市 / 大阪府大阪市
- デバイス・プロセス・設計フィジカル設計・レイアウト
- 中途
仕事内容
Job Description
-Chip/Block level floorplan, -Clock tree synthesis, -Place & Route, -RC extraction, -STA, timing closure, -IR/EM analysis and fix, -DRC/LVS/ERC analysis and fix, -Tape-out sign off. -APR Flow development
応募条件
必須
- BCH degree and above in EE/CS.
- Experienced in digital design/design flow/APR chip implementation related field.
- Experienced in advanced process nodes (28nm and below) -Familiar with Script languages (shell, python, TCL) or C/C++ -Familiar with APR tools (such as Cadence Innovus and Synopsys IC Compiler II ) & PPA analysis/boost methodology.
- Good customer-oriented attitude and communication skills.
- Good command of Japanese.
- Highly welcome candidates who have less experience but have good related design experience, working attitude and are self-motivated.
- English is a plus.
募集要項の原文
Qualifications -BCH degree and above in EE/CS. -Experienced in digital design/design flow/APR chip implementation related field. -Experienced in advanced process nodes (28nm and below) -Familiar with Script languages (shell, python, TCL) or C/C++ -Familiar with APR tools (such as Cadence Innovus and Synopsys IC Compiler II ) & PPA analysis/boost methodology. -Good customer-oriented attitude and communication skills. -Good command of Japanese. -Highly welcome candidates who have less experience but have good related design experience, working attitude and are self-motivated. -English is a plus. All qualified applicants will receive consideration for employment without r...
勤務条件
- 勤務地
- 神奈川県横浜市 / 大阪府大阪市
- 日本語
- 必須